\begin
Opdag hvorfor 18 millioner mennesker verden rundt stoler på Overleaf med deres arbejde.
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{\huge \bfseries \ttitle}\\[0.4cm] % Thesis title
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\large \textit{A thesis submitted in fulfillment of the requirements\\ for the degree of \degreename}\\[0.3cm] % University requirement text
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{\LARGE {\bf Dissertation Approval}}
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\vspace*{0.1in} \noindent This dissertation entitled {\large \bf \dissertationTitle} by {\bf \large \authornames}, Roll No. \authorrollno, is approved for the degree of {\large \bf \degree} from the Indian Institute of Technology Bombay.\\\\
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\hspace*{0.8cm}\ldots\ldots \ldots\ldots \ldots\ldots \ldots\ldots \hspace{2in} \ldots\ldots \ldots\ldots \ldots\ldots \ldots\ldots \\
\hspace*{0.4cm}\hspace*{0cm} Prof. xxxxxxxxx xxxxxxx \hspace{1.85in} Prof. xxxxxxx xxxxxxxxx\\
\hspace*{0.8cm}\hspace*{0.9cm} (Examiner 1) \hspace{2.8in} (Examiner 2)\\\\
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\hspace*{0.8cm}Defence Date: <Defence Date>\\\\
\hspace*{0.8cm}Place: IIT Bombay
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This is to certify that the dissertation entitled \textbf{``\dissertationTitle''}, submitted by \textbf{\authornames} to the Indian Institute of Technology Bombay, for the award of the degree of \textbf{\degree} in Electrical Engineering, is a record of the original, bona fide research work carried out by him under our supervision and guidance. The dissertation has reached the standards fulfilling the requirements of the regulations related to the award of the degree.
\par The results contained in this dissertation have not been submitted in part or in full to any other University or Institute for the award of any degree or diploma to the best of our knowledge.
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%\textbf{Prof. Akhilesh Kumar Maurya}\\
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\textbf{Prof. xxxxxx xxxxxxx}\\
Department of Electrical Engineering,\\
Indian Institute of Technology Bombay.
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\textbf{\LARGE {Declaration}}
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I declare that this written submission represents my ideas in my own words. Where others' ideas and words have been included, I have adequately cited and referenced the original source. I declare that I have adhered to all principles of academic honesty and integrity and have not misrepresented or fabricated, or falsified any idea/data/fact/source in my submission. I understand that any violation of the above will cause disciplinary action by the Institute and can also evoke penal action from the source which has thus not been properly cited or from whom proper permission has not been taken when needed.
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\textbf{\authornames} \\
Roll No.: \authorrollno \\
Date: <Date>\\
Place: IIT Bombay
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\textit{Index Terms} --- \lipsum[6]
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% ABBREVIATIONS
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{
% \textbf{SM} & \textbf{S}afety \textbf{M}argin\\
\textbf{CMOS} & \textbf{C}omplementary \textbf{M}etal \textbf{O}xide \textbf{S}emiconductor Field Effect Transistors\\
\textbf{SOI} & \textbf{S}ilicon-\textbf{o}n-\textbf{I}nsulator \\
\textbf{AI} & \textbf{A}rtificial \textbf{I}ntelligence \\
\textbf{ADC} & \textbf{A}nalog-to-\textbf{D}igital \textbf{C}onverter \\
\textbf{BTBT} & \textbf{B}and-\textbf{T}o-\textbf{B}and \textbf{T}unnelling \\
\textbf{CTDSM} & \textbf{C}ontinuous-\textbf{T}ime \textbf{D}elta-\textbf{S}igma \textbf{M}odulator \\
\textbf{SNN} & \textbf{S}piking \textbf{N}eural \textbf{N}etwork \\
\textbf{LIF} & \textbf{L}eaky \textbf{I}ntegrate-and-\textbf{F}ire \\
\textbf{SFA} & \textbf{S}pike-\textbf{F}requency \textbf{A}daptation \\
\textbf{DSM} & \textbf{D}elta-\textbf{S}igma \textbf{M}odulator \\
\textbf{PMOS} & \textbf{p}-type \textbf{MOS}FET \\
\textbf{NMOS} & \textbf{n}-type \textbf{MOS}FET \\
\textbf{SCL} & \textbf{S}emi-\textbf{C}onductor \textbf{L}aboratory, Government of India\\
\textbf{LSM} & \textbf{L}iquid \textbf{S}tate \textbf{M}achine \\
\textbf{LF} & \textbf{L}oop \textbf{F}ilter \\
\textbf{RC} & \textbf{R}esistor-\textbf{C}apacitor \\
\textbf{UGF} & \textbf{U}nity-\textbf{G}ain \textbf{F}requency \\
\textbf{SR} & \textbf{S}lew \textbf{R}ate \\
\textbf{DAC} & \textbf{D}igital-to-\textbf{A}nalog \textbf{C}onverter \\
\textbf{NTF} & \textbf{N}oise \textbf{T}ransfer \textbf{F}unction \\
\textbf{GF45RFSOI} & \textbf{G}lobal\textbf{F}oundaries \textbf{45} nm \textbf{RF} \textbf{SOI} \\
\textbf{MOSFET} & \textbf{M}etal \textbf{O}xide \textbf{S}emiconductor \textbf{F}ield \textbf{E}ffect \textbf{T}ransistor \\
\textbf{DCR} & \textbf{D}uty-\textbf{C}ycled \textbf{R}esistor \\
\textbf{DC} & \textbf{D}irect \textbf{Current} \\
\textbf{RS} & \textbf{R}eset-\textbf{S}et \\
\textbf{FFT} & \textbf{F}ast \textbf{F}ourier \textbf{T}ransform \\
\textbf{SFDR} & \textbf{S}purious-\textbf{F}ree \textbf{D}ynamic \textbf{R}ange \\
\textbf{SNDR} & \textbf{S}ignal-to-\textbf{N}oise-and-\textbf{D}istortion \textbf{R}atio \\
\textbf{ENOB} & \textbf{E}ffective \textbf{N}umber-\textbf{o}f-\textbf{B}its \\
\textbf{OSR} & \textbf{O}ver\textbf{s}ampling \textbf{R}atio \\
\textbf{FoM} & \textbf{F}igure \textbf{o}f \textbf{M}erit \\
\textbf{DTDSM} & \textbf{D}iscrete-\textbf{T}ime \textbf{D}elta-\textbf{S}igma \textbf{M}odulator \\
\textbf{ERBW} & \textbf{E}ffective \textbf{R}esolution \textbf{B}and\textbf{w}idth \\
\textbf{BW} & \textbf{B}and\textbf{w}idth \\
\textbf{MOS} & \textbf{M}etal \textbf{O}xide \textbf{S}emiconductor \\
\textbf{SoC} & \textbf{S}ystem-\textbf{o}n-a-\textbf{C}hip \\
\textbf{ANN} & \textbf{A}rtificial \textbf{N}eural \textbf{N}etwork \\
\textbf{RNN} & \textbf{R}ecurrent \textbf{N}eural \textbf{N}etwork \\
\textbf{PseudoR} & \textbf{Pseduo}-\textbf{R}esistor \\
\textbf{PDK} & \textbf{P}rocess \textbf{D}esign \textbf{K}it \\
\textbf{IoT} & \textbf{I}nternet \textbf{o}f \textbf{T}hings \\
\textbf{HH} & \textbf{H}odgkin-\textbf{H}uxley \\
\textbf{AdEx} & \textbf{Ad}aptive \textbf{Ex}ponential Integrate-and-Fire \\
\textbf{VLSI} & \textbf{V}ery-\textbf{L}arge-\textbf{S}cale \textbf{I}ntegration \\
\textbf{MeLoDe} & \textbf{Me}mory, \textbf{Lo}gic Device and \textbf{De}sign \\
\textbf{ISCAS} & IEEE \textbf{I}nternational \textbf{S}ymposium on \textbf{C}ircuits \textbf{a}nd \textbf{S}ystems \\
}
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% SYMBOLS
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\chead{\emph{Symbols}} % Set the left side page header to "Symbols"
\listofnomenclature{lll} % Include a list of Symbols (a two column table)
{
$mV_{pp}$ & Millivolt peak-to-peak \\
$I_{in}$ & Input current \\
$V_{GS}$ & Gate-source voltage \\
$V_{th}$ & Threshold voltage \\
$I_{DS}$ & Drain-source current \\
$g_m$ & MOSFET Self-Transconductance \\
$V_{S}$ & Source voltage \\
$V_{G}$ & Gate voltage \\
$V_{D}$ & Drain voltage \\
$M_{(.)}$ & MOSFET labelled (.) \\
$FoM_{W}$ & Walden Figure-of-Merit \\
$FoM_{SNDR}$ & Schreier Figure-of-Merit \\
$FoM_{A}$ & Area * Walden Figure-of-Merit \\
$R_{(.)}$ & Resistor labelled (.) \\
$V_{tune}$ & Tuning terminal of a tunable Pseudo-resistor \\
$V_{control}$ & Control terminal for our proposed Pseudo-resistor neuron \\
$d\_tolXfet\_bc$ & Thick-oxide 472 nm length body contact device (X=n/p for NMOS/PMOS) \\
$C_{membrane}$ & Neuron membrane capacitance \\
$C_{sfa}$ & Spike-frequency adaptation capacitance \\
}
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% THESIS CONTENT - CHAPTERS
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\pagestyle{fancy} % Return the page headers back to the "fancy" style
% Include the chapters of the thesis as separate files from the Chapters folder
% Uncomment the lines as you write the chapters
\input{Chapters/Chapter_1/Chapter1}
\part{My part1 label}
\label{part:part1}
\fancyhead[EC]{Part I. \emph{header label1}} %
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\input{Chapters/Chapter_3/Chapter3}
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%\input{Appendices/AppendixD}
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% BIBLIOGRAPHY
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\label{References}
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\clearpage
\section*{Publications by the candidate}
\begin{enumerate}
\item A. Raut, A. Kadam, A. Singh, L. Somappa, M. S. Baghini and U. Ganguly, "A sub-100 nW Power, Compact CTDSM with a Band-to-Band Tunnelling Loop Filter," in \textit{2024 IEEE International Symposium on Circuits and Systems (ISCAS)} \{Presented in May 2024; Conference proceedings yet to be published\}
\end{enumerate}
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\include{Acknowledgements}
\end{document}