This is a template for BSc and MSc theses (in Greek) for the School of Informatics students of the Aristotle University of Thessaloniki (AUTH).
Disclaimer: This template is designed by the Datalab group specifically for the students under the supervision of Prof. Athena Vakali.
Datalab (Data and Web Science Lab) - Aristotle University of Thessaloniki
This document describes the development of a small processor done as a high school self-learning project using the Verilog programming language, a software-based simulator, and FPGA hardware. This processor was made as a learning exercise and is not necessarily efficient, reliable, or compliant with best-practices. I would like to additionally thank the many helpful members of the ##fpga channel on the Freenode IRC network for their helpful tips and expertise.